JEDEC JESD 22-A117B

Description

This method establishes a standard procedure for determining the data cycling endurance and data retention capability of non-volatile memory cells. It is intended as a qualification and monitor test procedure. This test is also applicable to FLASH EEPROM integrated circuits and Erasable Programmable Logic Devices (EPLD) with embedded EEPROM or FLASH memory.

Product Details

Published:

03/01/2009

Number of Pages:

22

File Size:

1 file , 170 KB

Note:

This product is unavailable in Russia, Ukraine, Belarus