Name: ASTM F1392-00 PDF - Norm Library
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1.1 This test method covers the measurement of net carrier density and net carrier density profiles in epitaxial and polished bulk silicon wafers in the range from about 4 X 10 13 to about 8 X 10 16 carriers/cm (resistivity range from about 0.1 to about 100 [omega][dot]cm in -type wafers and from about 0.24 to about 330 [omega][dot]cm in -type wafers).

1.2 This test method requires the formation of a Schottky barrier diode with a mercury probe contact to an epitaxial or polished wafer surface. Chemical treatment of the silicon surface may be required to produce a reliable Schottky barrier diode (1). The surface treatment chemistries are different for – and -type wafers. This test method is sometimes considered destructive due to the possibility of contamination from the Schottky contact formed on the wafer surface; however, repetitive measurements may be made on the same test specimen.

1.3 This test method may be applied to epitaxial layers on the same or opposite conductivity type substrate. This test method includes descriptions of fixtures for measuring substrates with or without an insulating backseal layer.

1.4 The depth of the region that can be profiled depends on the doping level in the test specimen. Based on data reported by Severin (1) and Grove (2), Fig. 1 shows the relationships between depletion depth, dopant density, and applied voltage together with the breakdown voltage of a mercury silicon contact. The test specimen can be profiled from approximately the depletion depth corresponding to an applied voltage of 1 V to the depletion depth corresponding to the maximum applied voltage (200 V or about 80% of the breakdown voltage, whichever is lower). To be measured by this test method, a layer must be thicker than the depletion depth corresponding to an applied voltage of 2 V.

1.5 This test method is intended for rapid carrier density determination when extended sample preparation time or high temperature processing of the wafer is not practical.

Note 1-Test Method F419 is an alternative method for determining net carrier density profiles in silicon wafers from capacitance-voltage measurements. This test method requires the use of one of the following structures: ( ) a gated or ungated p-n junction diode fabricated using either planar or mesa technology or ( ) an evaporated metal Schottky diode.

1.6 This test method provides for determining the effective area of the mercury probe contact using polished bulk reference wafers that have been measured for resistivity at 23&degC in accordance with Test Method F84 (Note 2). This test method also includes procedures for calibration of the apparatus for measuring both capacitance and voltage.

Note 2-An alternative method of determining the effective area of the mercury probe contact that involves the use of reference wafers whose net carrier density has been measured using fabricated mesa or planar p-n junction diodes or evaporated Schottky diodes is not included in this test method but may be used if agreed upon by the parties to the test.

1.7 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in 7.1 (Note 4), 7.2, 7.10.3 (Note 8), 8.2, 11.5.1 (Note 18), 11.6.3, and 11.6.5.