JEDEC JEP156

$40.00

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
standard by JEDEC Solid State Technology Association, 03/01/2009

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Description

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.

Product Details

Published:
03/01/2009
Number of Pages:
24
File Size:
1 file , 150 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus