JEDEC JEP156A

Description

JEDEC JEP156A – CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.

Product Details

Published:

03/01/2018

Number of Pages:

24

File Size:

1 file , 85 KB

Note:

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