JEDEC JESD252

JEDEC JESD252

$32.00

SERIAL FLASH RESET SIGNALING PROTOCOL
standard by JEDEC Solid State Technology Association, 10/01/2018

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Description

JEDEC JESD252 is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin.

Product Details

Published:
10/01/2018
Number of Pages:
12
File Size:
1 file , 160 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus

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