JEDEC JESD252.01

JEDEC JESD252.01

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Serial Flash Reset Signaling Protocol

Published by Publication Date Number of Pages
JEDEC 04/01/2021 12
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JEDEC JESD252.01 – Serial Flash Reset Signaling Protocol

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

Product Details

Published:
04/01/2021
Number of Pages:
12
File Size:
1 file , 340 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus

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