JEDEC JESD28-A

JEDEC JESD28-A

$35.00

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS

Published by Publication Date Number of Pages
JEDEC 12/01/2001 18
PDF FormatPDF FormatMulti-User-AccessMulti-User AccessPrintablePrintableOnline downloadOnline Download
Category:

Description

JEDEC JESD28-A – A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS

This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process.

Product Details

Published:
12/01/2001
Number of Pages:
18
File Size:
1 file , 60 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus

In Demand Now